In performing floating point computations in a floating point unit of a data processing system, it is desirable to reduce the cost of components required for such computations without increasing the time for performing a particular computation operation thereof and/or to shorten the overall computation time for certain operations as effectively as possible without unduly increasing the overall cost in structure or operation of the unit. Thus, for example, it is desirable to improve conventionally used techniques for performing mantissa subtraction operations, for performing normalization operations, and for performing division operations. Conventional techniques often take several operating cycles for such operations or require too many costly circuit elements to achieve the desired speed of operation and it is desirable to be able to perform such operations within one or a few cycles or with fewer components if possible.
In performing a sign/magnitude mantissa subtraction operation, for example, conventional techniques utilize multi-stage propagate/generate carry techniques for producing a subtraction result, e.g., a subtraction of operands A and B, algebraically represented by (A-B), and then utilize a complete redundant set of propagate/generate carry stages for producing the negative result, i.e., (B-A). The highest order carry-out bit of the (A-B) process is then used to determine which result to select in accordance with well-known binary arithmetic techniques. The need for a complete redundant set of propagate/generate carry stages undesirably increases the cost of the overall system in performing such operation. Other techniques which have been proposed to reduce costs by using fewer components have undesirably increased the overall time needed to perform the operation. It is desirable to perform the operations at as low a cost as possible without increasing the time required for the performance thereof.
Further, in performing normalization techniques on exponent and mantissa results, conventional approaches utilize priority encoder circuitry for analyzing the overall exponent computation result in order to determine the number of leading zeroes therein. Once the number of leading zeroes is determined, such number is subtracted from the exponent value and the mantissa value is shifted to the left to eliminate the leading zeroes in accordance with well-known normalization techniques. The use of a priority encoder to operate upon the overall result in order to detect the number of leading zeroes has been found to undesirably increase the overall time needed for such operation. It is desirable therefore to determine the number of leading zeroes in a manner which would substantially reduce the conventionally required normalization time without unduly increasing the cost thereof.
Further, in performing division operations using higher radix techniques, i.e., higher than radix 2, one of the quantities required to be obtained in the divisional algorithm is the value of the quotient (Q) times the remainder (REMR) subtracted from the remainder (REMR) which quantity is normally obtained by prestoring values of Q*REMR and obtaining the desired prestored value for a plurality of values of Q and REMR. High radix computation techniques are well known to the art. Once the prestored value of Q*REMR is accessed from the memory region where it is pre-stored, it is subtracted from REMR and the division operation is completed. Such a technique requires a relatively large amount of time for the pregeneration of prestored Q*REMR values and a relatively large storage region, therefor. Moreover, the accessing of the desired quantity (REMR -Q*REMR) therefrom and the subtraction thereof from the remainder using high radix techniques normally takes a relatively long time. It would be desirable to perform such overall operations in a much shorter time and to avoid the need for such a large storage region for such purpose.